As semiconductor trends continue toward decreased size and increased packaging density, every aspect of semiconductor fabrication processes is scrutinized in an attempt to maximize efficiency in semiconductor fabrication and throughput. Many factors contribute to fabrication of a semiconductor. For example, at least one photolithographic process can be used during fabrication of a semiconductor. This particular factor in the fabrication process is highly scrutinized by the semiconductor industry in order to improve packaging density and precision in semiconductor structure.
Lithography is a process in semiconductor fabrication that generally relates to transfer of patterns between media. More specifically, lithography refers to transfer of patterns onto a thin film that has been deposited onto a substrate. The transferred patterns then act as a blueprint for desired circuit components. Typically, various patterns are transferred to a photoresist (e.g., radiation-sensitive film), which is the thin film that overlies the substrate during an imaging process described as “exposure” of the photoresist layer. During exposure, the photoresist is subjected to an illumination source (e.g. UV-light, electron beam, X-ray), which passes through a pattern template, or reticle, to print the desired pattern in the photoresist. Upon exposure to the illumination source, radiation-sensitive qualities of the photoresist permit a chemical transformation in exposed areas of the photoresist, which in turn alters the solubility of the photoresist in exposed areas relative to that of unexposed areas. When a particular solvent developer is applied, exposed areas of the photoresist are dissolved and removed, resulting in a three-dimensional pattern in the photoresist layer. This pattern is at least a portion of the semiconductor device that contributes to final function and structure of the device, or wafer.
Techniques, equipment and monitoring systems have concentrated on preventing and/or decreasing defect occurrence within lithography processes. For example, aspects of resist processes that are typically monitored can comprise: whether the correct mask has been used; whether resist film qualities are acceptable (e.g., whether resist is free from contamination, scratches, bubbles, striations, . . . ); whether image quality is adequate (e.g., good edge definition, line-width uniformity, and/or indications of bridging); whether critical dimensions are within specified tolerances; whether defect types and densities are recorded; and/or whether registration is within specified limits; etc. Such defect inspection task(s) have progressed into automated system(s) based on both automatic image processing and electrical signal processing.
Imprint lithography uses a patterned mask to “imprint” a pattern on a resist at a 1:1 feature size ratio. Thus, imprint mask integrity must be maintained throughout the lithography process because any flaw or structural defect present on a patterned imprint mask can be indelibly transferred to underlying layers during imprinting of a photoresist. One example of an undesirable structural defect is line-edge roughness (LER). LER refers to variations on sidewalls of features, which can result in variations of LER in the patterned photoresist and increased critical dimensions (CDs). Many factors can contribute to LER in the an imprint mask pattern, such as LER on chrome patterns residing on the reticle, image contrast in a system that generates the mask pattern, an etch process that can be used to pattern the mask, inherent properties and/or weaknesses of the mask materials, and/or the mask processing method. Additionally, LER appearing in fabricated structures can result from damage to the patterned resist during an etch process.
Current methods of pattern line formation on an imprint mask typically produce LER as an undesirable side effect. As lithographic techniques are pushed to their limits, smaller and smaller CDs are desired to maximize chip performance. Thus, chip manufacture is governed largely by wafer CD, which is defined as the smallest allowable width of, or space between, lines of circuitry in a semiconductor device. As methods of wafer manufacture are improved, wafer CD is decreased, which in turn requires finer and finer line edges to be produced. Line edges having a roughness that was acceptable just a year ago can detrimentally affect an imprint mask exhibiting today's critical dimension standards, which in turn can cause chip performance to deteriorate. Furthermore, as CD decreases, LER becomes increasingly difficult to avoid.